Technology

Aspinity Provides Ultra-Low-Power Processing

From smart phones and wearables to industrial monitoring and the broader Internet of Things, demand for sensor content continues to increase. Whether those sensors are enabling voice control, health tracking, or the next generation of apps, all sensor data are important. Devices must manage this data explosion without exploding the power consumption or the cost of the device, and Aspinity has the solution.

Aspinity’s revolutionary innovations enable data to be processed at the sensor in the native analog form. By extracting application-relevant characteristics prior to digitizing sensor data, Aspinity moves data analytics to the front of the signal chain. Examples include activation of a digital speech recognizer using a high-accuracy analog voice detector, or analog analysis of vibrational modes for industrial equipment monitoring. In all of these examples, Aspinity’s efficient pre-digital data analytics reduce the overall power and cost.

Analog data analytics are made possible with Aspinity’s innovations in programmable analog and experience developing analog algorithms. Aspinity’s programmable capabilities enable rapid development of analog algorithms for various applications. These algorithms can then be pushed to custom silicon with enough programmable overhead to allow in-product updates. Aspinity’s portfolio includes efficient analog algorithms that match the performance of state-of-the-art digital algorithms. See the Applications page for specific examples.


Aspinity ASP Architecture

At the heart of Aspinity’s solution is the Reconfigurable Analog/Mixed-Signal Processor (RAMP) --- a scalable, deployable, and programmable analog signal processor (ASP) core capable of supporting sophisticated data analysis algorithms for a multitude of applications. The RAMP architecture enables digital signal processing tasks to be replicated in analog—where they can process data more accurately and completely at a much lower power draw.

RAMP
                      Architecture
Aspinity’s innovations leverage the large-signal characteristics of a small number of transistors to field an architecture of modular, parallel, and continuously operating analog blocks that are configurable for sensor interfacing, signal processing, and decision making. Each of these blocks are implemented in a much smaller footprint than a traditional analog block, and remove the inefficiencies resulting from digitizing analog sensor data for digital processing. In the end, the architecture can reduce system power by an order of magnitude, while enabling continuous and always-on processing of analog data, all at a much higher accuracy and lower cost than digital processing solutions in use today.


RAMP IC

RAMP IC Aspinity has proven its solution in silicon with the release of its RAMP1 integrated circuit (IC). The IC includes complex analog-centric circuits, realized in a physical form that can be configured (programmed) automatically for a specific application. Current analog/mixed-signal design methodologies require an extended design and physical implementation effort; however, the RAMP IC is a silicon device ready for deployment that can be rapidly programed (and reprogrammed) and ultimately reduce the cost and turnaround time of analog and mixed-signal design. The RAMP IC can be used as an intelligent “wake-up” device, or replace a complete digital-processing system altogether. Since the RAMP is an analog implementation, it does not require a clock or memory as seen with digital implementations, and draws ~10uA continuously during always-on operation. The IC is implemented in a standard CMOS process without process variants or process technology adjustments as required with other analog designs.


Programming Aspinity’s RAMP

Digital processor architectures are much different than Aspinity’s analog processor architecture; however, the programming process is similar. The programming of the RAMP involves 3 primary pieces—configuration, programming, and calibration—in a self-contained algorithm that can be loaded over a simple serial interface. Firstly, the functional blocks/processing circuits needed for the application are “configured” via a switch fabric. Then, depending on the chosen functional blocks and the application requirements, each block is “programmed” with a set of coefficients that will enable the specific blocks to accurately perform their tasks in the signal processing chain. Finally, because of the complex nature of analog circuits and the variations seen in process technologies, a calibration scheme is employed to address the process-related inconsistencies in the specific blocks. The resultant algorithm can be modified and loaded into the RAMP multiple times, even in a deployed environment.

Architecture Comparison


Development Environment and Demo Board

Aspinity provides a demonstration board for the RAMP IC and a software environment to program the RAMP IC. The methodology provides the application developer with the ability to accomplish the 3 programming tasks previously discussed, including the selection and assembly of the modular functional blocks in the RAMP IC. This enables fast prototyping for applications, with deployable hardware, and lets application developers explore system-level implementation with the final hardware and software algorithms. The board provides multiple types of sensor inputs, as well as a microcontroller and other interfaces.

RAMP
                      Development Board