Today’s sensor systems collect data from the environment and convert (digitize) it for local analysis by embedded digital processors or wireless transmission to the cloud for further analysis. This is fine for lower-bandwidth applications such as fitness trackers, motion detectors, and GPS systems, as the data gathering process can be turned on and off (duty cycled) to save power without impacting the application. For higher-bandwidth applications, such as voice, all sound input is critical and must be processed to determine voice - duty cycling is not the answer. For these applications, the primary pain point is the power to digitize all of the sound, all of the time, in order to analyze for voice and subsequently for wakewords and commands.
Much like the senses and the initial receptors of the brain, Aspinity’s technology provides early and efficient intelligence gathering to make the overall system more efficient. This efficiency is realized with less data digitized and less power expended – much like our efficient human sensory processing systems. The truly revolutionary aspect of Aspinity’s innovations is that this early intelligence gathering can be mimicked in computational electronics, well before energy is wasted digitizing data that is irrelevant to the application at hand. The brain does not waste energy processing conversational speech if no voice is present/no one is talking.
Aspinity’s team has deep expertise in the study of neuromorphic and computational electronics and have successfully implemented integrated circuits (ICs) that support configurable analog structures with efficient algorithms. The approach has been to combine key aspects of neuromorphic structures (efficient weight-storage memory & analog neural networks) as well as traditional field-programmable array characteristics to build an easily deployable IC. Further innovations enable the reduction in size and power of these analog sub-blocks. The end result is an architecture that can replicate traditional DSP tasks and algorithms in analog, but at much higher efficiencies to the system.
Aspinity ASP Architecture
At the heart of Aspinity’s solution is the Reconfigurable Analog/Mixed-Signal Processor (RAMP)—a scalable, deployable, and programmable analog signal processor (ASP) core capable of supporting sophisticated data-analysis algorithms for a multitude of applications. The RAMP architecture enables digital signal processing tasks to be replicated in analog—where they can process data more accurately and completely at a much lower power draw.
Aspinity’s innovations leverage the large-signal characteristics of a small number of transistors to field an architecture of modular, parallel, and continuously operating analog blocks that are configurable for typical analog tasks such sensor interfacing, signal processing, and data conversion, but also more complex tasks such as feature extraction, event detection, and classification. Each of these blocks are implemented in a much smaller footprint than a traditional analog block, and remove the inefficiencies resulting from digitizing analog sensor data for digital processing. In the end, the architecture can reduce system power by an order of magnitude, while enabling continuous and always-on processing of analog data, all at a much higher accuracy and lower cost than digital processing solutions in use today
Aspinity has proven its solution in silicon with the release of its RAMP1 integrated circuit (IC). The IC includes complex analog-centric circuits, realized in a physical form that can be configured (programmed) automatically for a specific application. Current analog/mixed-signal design methodologies require an extended design and physical implementation effort; however, the RAMP IC is a silicon device ready for deployment that can be rapidly programed (and reprogrammed) and ultimately reduce the cost and turnaround time of analog and mixed-signal design.
The RAMP IC can be used as an intelligent “wake-up” device, or in some cases replace a complete digital-processing system altogether. Since the RAMP is an analog implementation, it does not require a clock or memory as seen with digital implementations, and draws ~10uA continuously during always-on operation. The IC is implemented in a standard CMOS process without process variants or process technology adjustments as required with other advanced analog designs.