Our Technology
Aspinity’s AnalogML™ is the most efficient NPU core for machine learning at the edge
AnalogML™ delivers state-of-the-art acceleration for machine learning in size and power constrained devices
- Best compute density: 0.86 TOPS/mm2
- Best compute efficiency: 300 TOPS/W
- Scalable compute fabric accommodates model needs for many applications (256 to 250+k parameters)
- Parameters embedded in compute elements to eliminate bottleneck
- Supports CNN, RNN, and other common layer types.
| Digital Accelerator | Analog In-Memory-Computing (IMC) | Aspinity AnalogML™ | |
|---|---|---|---|
| Data Movement | HighContinual movement of instructions, parameters, and intermediate data to/from cache | MediumParameters are embedded; still significant movement of instructions and intermediate data to/from cache | LowParameters and configuration (i.e., instructions) are embedded; Signals stream through |
| Parameter Precision | HighHigh-precision datatypes often supported | Low-MediumLimited to ≤ 8 bits precision, much less in many implementations | High10+ bit precision |
| MAC Precision | HighHigh-precision datatypes often supported | Low“Memory as compute” precision limited by linearity, noise, and mismatch | HighParameters co-located with compute allows linear multiplication circuits to be used |
| MAC Efficiency | Low1000’s of transistors and transfer instructions and operands from memory | Medium Efficient multiplication in analog; still fetch input vector from memory | HighEfficient multiplication in analog |
| NN Efficiency | LowData movement to/from memory | MediumMultiply is in memory but activation requires digital | HighMAC & activation all within analog circuitry |
| Robustness to Temperature & Manufacturing Variation | HighLimited issues with digital circuitry | LowChallenged with long signal chains | HighSilicon-proven and dynamic approach to on-the-fly trimming |
Precision Analog Parameters
High Performance Acceleration
Aspinity patented analog memory is co-located in circuits
10+ bits precision for storing parameters (weights, etc.)
Permanent and accurate parameter storage (no memory fetch)
Weight quantization not required to save power
Scalable NPU Architecture
- Tiled CAB (Configurable Analog Block) architecture can be sized for model needs
- CABs are software programmable to support a wide range of models and applications
- All-analog MAC and activation functions in each CAB (no digital conversions required)
- No interlayer data buffering
- High-precision analog parameters (10+ bit) located at compute circuit eliminates time and energy spent fetching datas
AnalogML™ enables robust and accurate immunity to analog variability
- Dynamic software-driven solution for on-the-fly variation trimming
- Leverages high-precision analog parameters for localized fine tuning/trimming
- Not susceptible to environmental or manufacturing variations
- Repeatable and consistent analog computing platform can be scaled to larger neural networks and smaller process nodes to meet the needs of next generation AI computing
Modern, easy-to-use Python based training and execution
Integration with common
ML frameworks
Simple and quick compilation
to AnalogML hardware
Supports CNN, RNN, and other common layer types
